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10 port SpaceWire router (AT7910E)

Download SpW_10X Router ASIC User Manual

A radiation tolerant SpaceWire router ASIC is being developed by University of Dundee, Austrian Aerospace, EADS Astrium GmbH and Atmel. The architecture of this device is illustrated in Fig. 1.

SpaceWire Router ASIC Architecture

Fig. 1: SpaceWire Router ASIC Architecture

There are eight SpaceWire ports, two external parallel ports and an internal configuration port in the SpaceWire router. A low latency, worm-hole routing, non-blocking, crossbar switch enables packets arriving at any SpaceWire port, external port or generated in the configuration port to be directed out of any other SpaceWire or external port, or to be routed to the configuration port.

The SpaceWire ports are fully compliant with the SpaceWire standard [1] providing high-speed, bi-directional communications. The external ports each comprise an input FIFO and an output FIFO and can receive and send data characters and end of packet markers. A time-code port is also provided along with a time-counter to facilitate the propagation of time-codes [6]. When a valid time-code arrives at a router port it is sent out of all the other SpaceWire ports and a TICK_OUT signal is generated at the time-code port. The router can operate as a time-code master using the TICK_IN provided in the time-code port.

The configuration port is accessible via any of the SpaceWire or external ports. It contains registers which control the operation of the SpaceWire ports, external ports and the crossbar switch. The configuration port holds status registers for the various ports and the switch. These registers can be read using a configuration read command to determine the status of the router and to access error information. Status and error information can also be selected for output on several status pins. The routing table is accessed via the configuration port. The logical address port mappings and priority bits can be set in the routing table. The routing table is used to control group adaptive routing and priority arbitration in the crossbar switch.

The SpaceWire router has first been implemented in Xilinx Virtex E and Virtex-2 devices. The SpaceWire ports operate at a maximum data signaling rate of 200 Mbits/s. The Virtex-2 device is fully compliant with the SpaceWire standard [1] and is functionally representative of the SpaceWire router ASIC.

The SpaceWire Router is now also implemented as an ASIC (SpW_10X or AT7910E) in the Atmel MH1RT gate array technology that uses a 0.35 Ám CMOS process with a radiation tolerance of up to 300k rad as well as latch-up immunity up to 80 MeV/mg/cm2. The data rate of the SpaceWire link interfaces ranges from 2 to 200 Mbit/s, where LVDS I/Os integrated onto the chip are used. Its power consumption is at the maximum data rate about 4 W. The chip operates from a single supply voltage of 3.3V (▒0.3V). The package is a 196 pin ceramic Metric Quad Flat Package with 25 mil pin spacing.

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