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SpW-RTC (AT7913E)

SAAB Space AB (S) as prime contractor together with Gaisler Research AB (S) as subcontractor initiated the development of the SpaceWire Remote Terminal Controller (SpW-RTC) ASIC in 2005. The System On Chip (SoC) architecture comprises a set of IP cores where the Leon2-FT Integer Unit, HurriCANe CAN core, and the SpW CoDec has been provided under ESA license.

The SpaceWire-RTC device includes an embedded microprocessor, a CAN bus controller, ADC/DAC interfaces for analogue acquisition/conversion, standard interfaces and resources (UARTs, timers, general purpose input output).

The SpaceWire Remote Terminal Controller (RTC) device can be used as a bridge between the SpaceWire network and the CAN bus, providing a fully integrated system. Additional features are provided to carter for autonomy of remote terminals and to relieve the central processing chain of repetitive standard acquisitions and management duties. The SpaceWire-RTC device can be used both in non-intelligent nodes and in nodes with local intelligence.

The SpaceWire-RTC device can be operated stand-alone or with a number of external devices such as SRAM, PROM and FIFO memories, ADC and DAC converters. The device can be managed locally by the on-chip processor, or remotely via its SpaceWire link interfaces. SpaceWire-RTC device can operate as a single-chip system, with software being uploaded to its on-chip memory via the SpaceWire link interface, forming a compact solution for remotely controlled applications. Or it can operate in a full-size system, with software being decompressed from local PROM and executed from multiple fast and wide SRAM memory banks. The device provides scalability in terms of use of external devices and operating frequency.

SpaceWire-RTC ASIC Block Diagram

ASIC Validation

The validation activity for the SpaceWire RTC ASIC was completed first week of June 2008. This was an important step after manufacturing of the ASIC in which a set of validation tests were performed to ensure that the device was operating according to specifications. From these tests a number of performance indicators can be derived for a given system configuration.

Processor and FPU performance

To measure pure processor performance, the standard Dhrystone and Stanford benchmark tests were run. For a SpW-RTC ASIC with a 50 MHz core clock speed, the Dhrystone tests yield 34 MIPS. Floating point benchmarks show an average performance of 2.5 MFLOPS SpW to FIFO I/F throughput performance

SpaceWire-RTC Under Test

The above image shows the test set-up in which the FIFOs (dotted red circle) are connected in loopback. The two SpW interfaces (yellow circle) are also connected in loopback and both links are transferring data in full duplex at 200Mbit/s via the FIFO I/F. The theoretical ideal AMBA bus bandwidth, for a 30MHz core speed, is 32bit * 30MHz = 960 Mbit/s. A configuration set-up, where the two SpW links are connected in loopback as well as having an external loopback FIFO configuration, was used to test the maximum throughput performance between the SpW I/F and FIFO I/F. The test involved full duplex data transfers simultaneously for both links yielding total data transfer rate on the SpW links at 720Mbit/s. Taking into account the 20% SpW protocol overhead, the total AMBA bus transfer rate was 576Mbit/s between the two SpW I/Fs and the FIFO I/F.

Performance Test Application

A software application for a system configuration that resembles a typical scenario for the SpW-RTC was developed to derive performance figures. It involves executing the Dhrystone benchmark via of chip SRAM, full duplex data transfers from on-chip memory via loop backed SpaceWire links, data transfers from on-chip memory to external FIFO and back again, writing a 12bit value to DAC and read back via ADC interface, GPIO pulse generation and CAN bus traffic to external test equipment. Resulting performance figures were;

  • SpaceWire throughput was 587 Mbit/s (full duplex), with 96% internal on-chip AMBA Bus efficiency.
  • FIFO throughput was 295 Mbit/s, with 1,35 system clock cycles per byte.
  • The CAN throughput was 208 kbit/sec. The throughput was limited by loopback via host computer.
  • The number of ADC and DAC conversions was 784 pr. Second, each.
  • The number of GPIO pulses was 784 pr. second.
  • The total number of interrupts was 7965 per second.
  • The Dhrystone benchmark gave 27.9 MIPS (compared to 34,4 MIPS)

The successful completion of the extensive validation tests marks a significant milestone in the SpW-RTC development cycle.

ASIC technology and Package

The SpW-RTC ASIC is manufactured using Atmel 0.18um ATC18RHA technology which guarantees no single event latch up below a LET threshold of 80 Mev/mg/cm2. It is a CMOS based technology using 5 metal layers and specifications for the SpW-RTC are 3.3V for peripheral buffers and 1.8V for internal core signals. The SpW RTC ASIC comes in a grounded lid MCGA349 package with 50mil pin spacing.

SpaceWire RTC ASIC

For more information contact: spacewire.components(at)esa.int

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