h t t p : / / s p a c e w i r e . e s a . i n t
Click Here for Printable View

GR718 SpaceWire Router

GR718 SpaceWire Router Architecture

Fig. 1: GR718 SpaceWire Router Architecture

The SpaceWire Router ASIC architecture is centred around a non-blocking switch matrix which can connect any input port to any output port. The device implements 18 external SpaceWire ports, where 16 have on-chip LVDS transceivers and two have LVTTL interfaces. All mandatory and optional routing features defined in the SpaceWire standard are supported. All configuration and status accesses are handled through the configuration port (port 0) which can be accessed using the RMAP protocol from any of the other ports, or through the JTAG or UART debug interfaces connected to the on-chip AMBA bus.

The SpaceWire router has been manufactured in 180nm UMC CMOS technology, based on the DARE+ library from IMEC (BE). The technology is radiation hard, with at least 300 krad(Si) TID tolerance, high SEL tolerance and SEU hardened flip-flops. The package used is a 256 CGFP. The target speed for the SpaceWire links was 200Mbps, and therefore the link speed specified in the data sheet is 200Mbps. Nevertheless, during functional testing and validation the ASIC has been found to operate successfully at 240Mbps. The device uses 1.8V and 3.3V suppy, and the typical power consumption is 3W when running all 18 SpaceWire ports in 200Mbps.

Copyright 2000 - 2017 © European Space Agency. All rights reserved.
If you have any questions or comments regarding this website, please contact the webmaster.